4篇
您的检索式：作者名="Vaibhav Neema"
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| 1 | DOIND: a technique for leakage reduction in nanoscale domino logic circuits显示文摘A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic. | Ambika Prasad Shah Vaibhav Neema Shreeniwas Daulatabad | 2016 | Journal of Semiconductors2016，37，5： | 2 |
| 2 | Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET显示文摘We propose a reliable asymmetric dual-k spacer with SiC source/drain(S/D)pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility(eMobility),current driving capabilities,transconductance(G_m)and subthreshold slope(SS).The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance.We analysed the variation in drive current for different values of carbon(C)mole fraction y in Si_(1-y)C_y.It is found that the mole fraction also helps to improve device lifetime,performance enhancement also pointed by transconductance variation with the gate length.All the simulations are performed in the 3-D Sentaurus TCAD tool.The proposed device structure achieved ION=2.17 mA/μm for Si_(0.3)C_(0.7) and found that Si_(0.5)C_(0.5) is more suitable for the perspective of a process variation effect for 14 nm as the gate length.We introduce reliability issues and their solutions for Si_(1-y)C_y FinFET for the first time. | Maisagalla Gopal Atul Awadhiya NANDakishor Yadav S.K.Vishvakarma Vaibhav Neema | 2018 | Journal of Semiconductors2018，39，10： | 0 |
| 3 | BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics显示文摘We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure Hf Al O and AlLaO_3 replace Si_3N_4 and the top SiO_2 layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time. | Sonal Jain Deepika Gupta Vaibhav Neema Santosh Vishwakarma | 2016 | Journal of Semiconductors2016，37，3： | 0 |
| 4 | Application of source biasing technique for energy efficient DECODER circuit design: memory array application显示文摘Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DE-CODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92%and static energy by 99.92%at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69%,dynamic PDP/EDP 65.03%and delay 57.25%at 1.2 V supply voltage. | Neha Gupta Priyanka Parihar Vaibhav Neema | 2018 | Journal of Semiconductors2018，39，4： | 0 |
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